TheAD9515featuresatwo-outputclockdistributionICinadesignthatemphasizeslowjitterandphasenoisetomaximizedataconverterperformance.Otherapplicationswithdemandingphasenoiseandjitterrequirementsalsobenefitfromthispart.
Therearetwoindependentclockoutputs.OneoutputisLVPECL,whiletheotheroutputcanbesettoeitherLVDSorCMOSlevels.TheLVPECLoutputoperatesto1.6GHz.Theotheroutputoperatesto800MHzinLVDSmodeandto250MHzinCMOSmode.
Eachoutputhasaprogrammabledividerthatcanbesettodividebyaselectedsetofintegersrangingfrom1to32.Thephaseofoneclockoutputrelativetotheotherclockoutputcanbesetbymeansofadividerphaseselectfunctionthatservesasacoarsetimingadjustment.
TheLVDS/CMOSoutputfeaturesadelayelementwiththreeselectablefull-scaledelayvalues(1.5ns,5ns,and10ns),eachwith16stepsoffineadjustment.
TheAD9515doesnotrequireanexternalcontrollerforoperationorsetup.Thedeviceisprogrammedbymeansof11pins(S0toS10)using4-levellogic.Theprogrammingpinsareinternallybiasedto⅓VS.TheVREFpinprovidesalevelof⅔VS.VS(3.3V)andGND(0V)providetheothertwologiclevels.
TheAD9515isideallysuitedfordataconverterclockingapplicationswheremaximumconverterperformanceisachievedbyencodesignalswithsubpicosecondjitter.
TheAD9515isavailableina32-leadLFCSPandoperatesfromasingle3.3Vsupply.Thetemperaturerangeis−40°Cto+85°C.