TheAD9510providesamulti-outputclockdistributionfunctionalongwithanon-chipPLLcore.Thedesignemphasizeslowjitterandlowphasenoiseinordertomaximizedataconverterclockingperformance.FourindependentLVPECLandfourLVDSclockoutputsoperateto1.2GHzand800MHzrespectively.OptionalCMOSclockoutputsavailableto250MHz.
ThePLLsectionconsistsofaprogrammablereferencedivider,R;alow-noisephasefrequencydetector,PFD;aprecisionchargepump,CP;andaprogrammablefeedbackdivider,N.ByconnectinganexternalVCXOorVCOtotheCLK2andCLK2Bpins,PLLoutputfrequenciesupto1.6GHzmaybesynchronizedtotheinputreference,REFIN.
TheclockdistributionsectionprovidesLVPECLoutputsandoutputsthatmaybeprogrammedtoeitherLVDSorCMOS.Eachoutputhasaprogrammabledivider,whichmaybebypassedorsettodividebyanyintegerupto32.
Eachdividerallowstheusertochangethephaseofoneclockoutputrelativetoanotherclockoutput.Thisphaseselectfunctionsasacoarsetimingadjustment.Someoutputsalsofeatureprogrammabledelayelementswithauser-selected,fullscalerangeto10ns.Thisfinetuningdelayblockisprogrammedwitha5-bitword,whichgivestheuser32possibledelaysfromwhichtochoose.
TheAD9510isideallysuitedfordataconverterclockingapplicationswheremaximumconverterperformanceisachievedwithsub-picosecondjitterencodesignals.
TheAD9510isavailableina64-leadLFCSPandisspecifiedfrom-40°Cto+85°C.Thepartmayberunfromasingle3.3Vsupply.UserswishingtoextendthevoltagerangeforexternalVCOsmayrunthechargepumpsupply,VCP,to5.5V.