TheAD800andAD802employasecondorderphase-lockedlooparchitecturetoperformclockrecoveryanddataretimingonNon-ReturntoZero,NRZ,data.Thisarchitectureiscapableofsupportingdataratesbetween20Mbpsand160Mbps.Theproductsdescribedherehavebeendefinedtoworkwithstandardtelecommunicationsbitrates.45MbpsDS-3and52MbpsSTS-1aresupportedbytheAD800-45andAD800-52respectively.155MbpsSTS-3orSTM-1aresupportedbytheAD802-155.
UnlikeotherPLL-basedclockrecoverycircuits,thesedevicesdonotrequireapreambleoranexternalVCXOtolockontoinputdata.Thecircuitacquiresfrequencyandphaselockusingtwocontrolloops.Thefrequencyacquisitioncontrolloopinitiallyacquirestheclockfrequencyoftheinputdata.Thephase-lockloopthanacquiresthephaseoftheinputdata,andensuresthephaseoftheoutputsignalstrackchangesinthephaseoftheoutputdata.Theloopdampingofthecircuitisdependentofthevalueofauserselectedcapacitor;thisdefinesjitterpeakingandperformanceandimpactsacquisitiontime.Thedevicesexhibit0.08dBjitterpeaking,andacquirelockonrandomorscrambleddatawithin4X105bitperiodswhenusingadampingfactorof5.
DuringtheprocessofacquisitionthefrequencydetectorprovidesaFrequencyAcquisition(FRAC)signalwhichindicatesthatthedevicehasnotyetlockedontotheinputdata.Thissignalisaseriesofpulseswhichoccuratthepointsofcycleslipbetweentheinputdataandthesynthesizedclocksignal.OncethecircuithasacquiredfrequencylocknopulsesoccurattheFRACoutput.
TheinclusionofapreciselytrimmedVCOinthedeviceeliminatestheneedforexternalcomponentsforsettingcenterfrequency,andtheneedfortrimmingofthosecomponents.TheVCOprovidesaclockoutputwithin±20%ofthedevicecenterfrequencyintheabsenceofinputdata.
TheAD800andAD802exhibitvirtuallynopatternjitter,duetotheperformanceofthepatentedphasedetector.Totalloopjitteris20°peak-to-peak.Jitterbandwidthisdictatedbymaskprogrammablefractionalloopbandwidth.TheAD800,usedfordatarates<90Mbps,hasbeendesignedwithnominalloopbandwidthof0.1%ofthecenterfrequency.TheAD802,usedfordataratesinexcessof90Mbps,hasaloopbandwidthof0.08%ofcenterfrequency.
Allofthedevicesoperatewithasingle+5Vor-5.2Vsupply.