12306火车票订票官网下载12346（Server）

ubuntu信息如下。

root@hanyw:~# root@hanyw:~# LSB_release -a No LSB modules are available. Distributor ID: Ubuntu Description: Ubuntu 22.04.1 LTS Release: 22.04 Codename: jammy root@hanyw:~# root@hanyw:~# root@hanyw:~# uname -r 5.15.0-53-generic

GCC帮助手册的第19小节，第12288~13288行，如下。

12228 Use a simple check for control speculation. This option is on by default. 12229 -msched-stop-bits-after-every-cycle 12230 Place a stop bit after every cycle when scheduling. This option is on by default. 12231 -msched-fp-mem-deps-zero-cost 12232 Assume that floating-point stores and loads are not likely to cause a conflict when placed into the same 12233 instruction group. This option is disabled by default. 12234 -msel-sched-dont-check-control-spec 12235 Generate checks for control speculation in selective scheduling. This flag is disabled by default. 12236 -msched-max-memory-insns=max-insns 12237 Limit on the number of memory insns per instruction group, giving lower priority to subsequent memory insns 12238 attempting to schedule in the same instruction group. Frequently useful to prevent cache bank conflicts. 12239 The default value is 1. 12240 -msched-max-memory-insns-hard-limit 12241 Makes the limit specified by msched-max-memory-insns a hard limit, disallowing more than that number in an 12242 instruction group. Otherwise, the limit is "soft", meaning that non-memory operations are preferred when 12243 the limit is reached, but memory operations may still be scheduled. 12244 LM32 Options 12245 These -m options are defined for the LatticeMico32 architecture: 12246 -mbarrel-shift-enabled 12247 Enable barrel-shift instructions. 12248 -mdivide-enabled 12249 Enable divide and modulus instructions. 12250 -mmultiply-enabled 12251 Enable multiply instructions. 12252 -msign-extend-enabled 12253 Enable sign extend instructions. 12254 -muser-enabled 12255 Enable user-defined instructions. 12256 M32C Options 12257 -mcpu=name 12258 Select the CPU for which code is generated. name may be one of r8c for the R8C/Tiny series, m16c for the 12259 M16C (up to /60) series, m32cm for the M16C/80 series, or m32c for the M32C/80 series. 12260 -msim 12261 Specifies that the program will be run on the simulator. This causes an alternate runtime library to be 12262 linked in which supports, for example, file I/O. You must not use this option when generating programs 12263 that will run on real hardware; you must provide your own runtime library for whatever I/O functions are 12264 needed. 12265 -memregs=number 12266 Specifies the number of memory-based pseudo-registers GCC uses during code generation. These pseudo- 12267 registers are used like real registers, so there is a tradeoff between GCC's ability to fit the code into 12268 available registers, and the performance penalty of using memory instead of registers. Note that all 12269 modules in a program must be compiled with the same value for this option. Because of that, you must not 12270 use this option with GCC's default runtime libraries. 12271 M32R/D Options 12272 These -m options are defined for Renesas M32R/D architectures: 12273 -m32r2 12274 Generate code for the M32R/2. 12275 -m32rx 12276 Generate code for the M32R/X. 12277 -m32r 12278 Generate code for the M32R. This is the default. 12279 -mmodel=small 12280 Assume all objects live in the lower 16MB of memory (so that their addresses can be loaded with the "ld24" 12281 instruction), and assume all subroutines are reachable with the "bl" instruction. This is the default. 12282 The addressability of a particular object can be set with the "model" attribute. 12283 -mmodel=medium 12284 Assume objects may be anywhere in the 32-bit address space (the compiler generates "seth/add3" instructions 12285 to load their addresses), and assume all subroutines are reachable with the "bl" instruction. 12286 -mmodel=large 12287 Assume objects may be anywhere in the 32-bit address space (the compiler generates "seth/add3" instructions 12288 to load their addresses), and assume subroutines may not be reachable with the "bl" instruction (the 12289 compiler generates the much slower "seth/add3/jl" instruction sequence). 12290 -msdata=none 12291 Disable use of the small data area. Variables are put into one of ".data", ".bss", or ".rodata" (unless 12292 the "section" attribute has been specified). This is the default. 12293 The small data area consists of sections ".sdata" and ".sbss". Objects may be explicitly put in the small 12294 data area with the "section" attribute using one of these sections. 12295 -msdata=sdata 12296 Put small global and static data in the small data area, but do not generate special code to reference 12297 them. 12298 -msdata=use 12299 Put small global and static data in the small data area, and generate special instructions to reference 12300 them. 12301 -G num 12302 Put global and static objects less than or equal to num bytes into the small data or BSS sections instead 12303 of the normal data or BSS sections. The default value of num is 8. The -msdata option must be set to one 12304 of sdata or use for this option to have any effect. 12305 All modules should be compiled with the same -G num value. Compiling with different values of num may or 12306 may not work; if it doesn't the linker gives an error message---incorrect code is not generated. 12307 -mdebug 12308 Makes the M32R-specific code in the compiler display some statistics that might help in debugging programs. 12309 -malign-loops 12310 Align all loops to a 32-byte boundary. 12311 -mno-align-loops 12312 Do not enforce a 32-byte alignment for loops. This is the default. 12313 -missue-rate=number 12314 Issue number instructions per cycle. number can only be 1 or 2. 12315 -mbranch-cost=number 12316 number can only be 1 or 2. If it is 1 then branches are preferred over conditional code, if it is 2, then 12317 the opposite applies. 12318 -mflush-trap=number 12319 Specifies the trap number to use to flush the cache. The default is 12. Valid numbers are between 0 and 12320 15 inclusive. 12321 -mno-flush-trap 12322 Specifies that the cache cannot be flushed by using a trap. 12323 -mflush-func=name 12324 Specifies the name of the operating system function to call to flush the cache. The default is 12325 _flush_cache, but a function call is only used if a trap is not available. 12326 -mno-flush-func 12327 Indicates that there is no OS function for flushing the cache. 12328 M680x0 Options 12329 These are the -m options defined for M680x0 and ColdFire processors. The default settings depend on which 12330 architecture was selected when the compiler was configured; the defaults for the most common choices are given 12331 below. 12332 -march=arch 12333 Generate code for a specific M680x0 or ColdFire instruction set architecture. Permissible values of arch 12334 for M680x0 architectures are: 68000, 68010, 68020, 68030, 68040, 68060 and cpu32. ColdFire architectures 12335 are selected according to Freescale's ISA classification and the permissible values are: isaa, isaaplus, 12336 isab and isac. 12337 GCC defines a macro "__mcfarch__" whenever it is generating code for a ColdFire target. The arch in this 12338 macro is one of the -march arguments given above. 12339 When used together, -march and -mtune select code that runs on a family of similar processors but that is 12340 optimized for a particular microarchitecture. 12341 -mcpu=cpu 12342 Generate code for a specific M680x0 or ColdFire processor. The M680x0 cpus are: 68000, 68010, 68020, 12343 68030, 68040, 68060, 68302, 68332 and cpu32. The ColdFire cpus are given by the table below, which also 12344 classifies the CPUs into families: 12345 Family : -mcpu arguments 12346 51 : 51 51ac 51ag 51cn 51em 51je 51jf 51jg 51jm 51mm 51qe 51qm 12347 5206 : 5202 5204 5206 12348 5206e : 5206e 12349 5208 : 5207 5208 12350 5211a : 5210a 5211a 12351 5213 : 5211 5212 5213 12352 5216 : 5214 5216 12353 52235 : 52230 52231 52232 52233 52234 52235 12354 5225 : 5224 5225 12355 52259 : 52252 52254 52255 52256 52258 52259 12356 5235 : 5232 5233 5234 5235 523x 12357 5249 : 5249 12358 5250 : 5250 12359 5271 : 5270 5271 12360 5272 : 5272 12361 5275 : 5274 5275 12362 5282 : 5280 5281 5282 528x 12363 53017 : 53011 53012 53013 53014 53015 53016 53017 12364 5307 : 5307 12365 5329 : 5327 5328 5329 532x 12366 5373 : 5372 5373 537x 12367 5407 : 5407 12368 5475 : 5470 5471 5472 5473 5474 5475 547x 5480 5481 5482 5483 5484 5485 12369 -mcpu=cpu overrides -march=arch if arch is compatible with cpu. Other combinations of -mcpu and -march are 12370 rejected. 12371 GCC defines the macro "__mcf_cpu_cpu" when ColdFire target cpu is selected. It also defines 12372 "__mcf_family_family", where the value of family is given by the table above. 12373 -mtune=tune 12374 Tune the code for a particular microarchitecture within the constraints set by -march and -mcpu. The 12375 M680x0 microarchitectures are: 68000, 68010, 68020, 68030, 68040, 68060 and cpu32. The ColdFire 12376 microarchitectures are: cfv1, cfv2, cfv3, cfv4 and cfv4e. 12377 You can also use -mtune=68020-40 for code that needs to run relatively well on 68020, 68030 and 68040 12378 targets. -mtune=68020-60 is similar but includes 68060 targets as well. These two options select the same 12379 tuning decisions as -m68020-40 and -m68020-60 respectively. 12380 GCC defines the macros "__mcarch" and "__mcarch__" when tuning for 680x0 architecture arch. It also 12381 defines "mcarch" unless either -ansi or a non-GNU -std option is used. If GCC is tuning for a range of 12382 architectures, as selected by -mtune=68020-40 or -mtune=68020-60, it defines the macros for every 12383 architecture in the range. 12384 GCC also defines the macro "__muarch__" when tuning for ColdFire microarchitecture uarch, where uarch is 12385 one of the arguments given above. 12386 -m68000 12387 -mc68000 12388 Generate output for a 68000. This is the default when the compiler is configured for 68000-based systems. 12389 It is equivalent to -march=68000. 12390 Use this option for microcontrollers with a 68000 or EC000 core, including the 68008, 68302, 68306, 68307, 12391 68322, 68328 and 68356. 12392 -m68010 12393 Generate output for a 68010. This is the default when the compiler is configured for 68010-based systems. 12394 It is equivalent to -march=68010. 12395 -m68020 12396 -mc68020 12397 Generate output for a 68020. This is the default when the compiler is configured for 68020-based systems. 12398 It is equivalent to -march=68020. 12399 -m68030 12400 Generate output for a 68030. This is the default when the compiler is configured for 68030-based systems. 12401 It is equivalent to -march=68030. 12402 -m68040 12403 Generate output for a 68040. This is the default when the compiler is configured for 68040-based systems. 12404 It is equivalent to -march=68040. 12405 This option inhibits the use of 68881/68882 instructions that have to be emulated by software on the 68040. 12406 Use this option if your 68040 does not have code to emulate those instructions. 12407 -m68060 12408 Generate output for a 68060. This is the default when the compiler is configured for 68060-based systems. 12409 It is equivalent to -march=68060. 12410 This option inhibits the use of 68020 and 68881/68882 instructions that have to be emulated by software on 12411 the 68060. Use this option if your 68060 does not have code to emulate those instructions. 12412 -mcpu32 12413 Generate output for a CPU32. This is the default when the compiler is configured for CPU32-based systems. 12414 It is equivalent to -march=cpu32. 12415 Use this option for microcontrollers with a CPU32 or CPU32 core, including the 68330, 68331, 68332, 68333, 12416 68334, 68336, 68340, 68341, 68349 and 68360. 12417 -m5200 12418 Generate output for a 520X ColdFire CPU. This is the default when the compiler is configured for 12419 520X-based systems. It is equivalent to -mcpu=5206, and is now deprecated in favor of that option. 12420 Use this option for microcontroller with a 5200 core, including the MCF5202, MCF5203, MCF5204 and MCF5206. 12421 -m5206e 12422 Generate output for a 5206e ColdFire CPU. The option is now deprecated in favor of the equivalent 12423 -mcpu=5206e. 12424 -m528x 12425 Generate output for a member of the ColdFire 528X family. The option is now deprecated in favor of the 12426 equivalent -mcpu=528x. 12427 -m5307 12428 Generate output for a ColdFire 5307 CPU. The option is now deprecated in favor of the equivalent 12429 -mcpu=5307. 12430 -m5407 12431 Generate output for a ColdFire 5407 CPU. The option is now deprecated in favor of the equivalent 12432 -mcpu=5407. 12433 -mcfv4e 12434 Generate output for a ColdFire V4e family CPU (e.g. 547x/548x). This includes use of hardware floating- 12435 point instructions. The option is equivalent to -mcpu=547x, and is now deprecated in favor of that option. 12436 -m68020-40 12437 Generate output for a 68040, without using any of the new instructions. This results in code that can run 12438 relatively efficiently on either a 68020/68881 or a 68030 or a 68040. The generated code does use the 12439 68881 instructions that are emulated on the 68040. 12440 The option is equivalent to -march=68020 -mtune=68020-40. 12441 -m68020-60 12442 Generate output for a 68060, without using any of the new instructions. This results in code that can run 12443 relatively efficiently on either a 68020/68881 or a 68030 or a 68040. The generated code does use the 12444 68881 instructions that are emulated on the 68060. 12445 The option is equivalent to -march=68020 -mtune=68020-60. 12446 -mhard-float 12447 -m68881 12448 Generate floating-point instructions. This is the default for 68020 and above, and for ColdFire devices 12449 that have an FPU. It defines the macro "__HAVE_68881__" on M680x0 targets and "__mcffpu__" on ColdFire 12450 targets. 12451 -msoft-float 12452 Do not generate floating-point instructions; use library calls instead. This is the default for 68000, 12453 68010, and 68832 targets. It is also the default for ColdFire devices that have no FPU. 12454 -mdiv 12455 -mno-div 12456 Generate (do not generate) ColdFire hardware divide and remainder instructions. If -march is used without 12457 -mcpu, the default is "on" for ColdFire architectures and "off" for M680x0 architectures. Otherwise, the 12458 default is taken from the target CPU (either the default CPU, or the one specified by -mcpu). For example, 12459 the default is "off" for -mcpu=5206 and "on" for -mcpu=5206e. 12460 GCC defines the macro "__mcfhwdiv__" when this option is enabled. 12461 -mshort 12462 Consider type "int" to be 16 bits wide, like "short int". Additionally, parameters passed on the stack are 12463 also aligned to a 16-bit boundary even on targets whose API mandates promotion to 32-bit. 12464 -mno-short 12465 Do not consider type "int" to be 16 bits wide. This is the default. 12466 -mnobitfield 12467 -mno-bitfield 12468 Do not use the bit-field instructions. The -m68000, -mcpu32 and -m5200 options imply -mnobitfield. 12469 -mbitfield 12470 Do use the bit-field instructions. The -m68020 option implies -mbitfield. This is the default if you use 12471 a configuration designed for a 68020. 12472 -mrtd 12473 Use a different function-calling convention, in which functions that take a fixed number of arguments 12474 return with the "rtd" instruction, which pops their arguments while returning. This saves one instruction 12475 in the caller since there is no need to pop the arguments there. 12476 This calling convention is incompatible with the one normally used on Unix, so you cannot use it if you 12477 need to call libraries compiled with the Unix compiler. 12478 Also, you must provide function prototypes for all functions that take variable numbers of arguments 12479 (including "printf"); otherwise incorrect code is generated for calls to those functions. 12480 In addition, seriously incorrect code results if you call a function with too many arguments. (Normally, 12481 extra arguments are harmlessly ignored.) 12482 The "rtd" instruction is supported by the 68010, 68020, 68030, 68040, 68060 and CPU32 processors, but not 12483 by the 68000 or 5200. 12484 The default is -mno-rtd. 12485 -malign-int 12486 -mno-align-int 12487 Control whether GCC aligns "int", "long", "long long", "float", "double", and "long double" variables on a 12488 32-bit boundary (-malign-int) or a 16-bit boundary (-mno-align-int). Aligning variables on 32-bit 12489 boundaries produces code that runs somewhat faster on processors with 32-bit busses at the expense of more 12490 memory. 12491 Warning: if you use the -malign-int switch, GCC aligns structures containing the above types differently 12492 than most published application binary interface specifications for the m68k. 12493 Use the pc-relative addressing mode of the 68000 directly, instead of using a global offset table. At 12494 present, this option implies -fpic, allowing at most a 16-bit offset for pc-relative addressing. -fPIC is 12495 not presently supported with -mpcrel, though this could be supported for 68020 and higher processors. 12496 -mno-strict-align 12497 -mstrict-align 12498 Do not (do) assume that unaligned memory references are handled by the system. 12499 -msep-data 12500 Generate code that allows the data segment to be located in a different area of memory from the text 12501 segment. This allows for execute-in-place in an environment without virtual memory management. This 12502 option implies -fPIC. 12503 -mno-sep-data 12504 Generate code that assumes that the data segment follows the text segment. This is the default. 12505 -mid-shared-library 12506 Generate code that supports shared libraries via the library ID method. This allows for execute-in-place 12507 and shared libraries in an environment without virtual memory management. This option implies -fPIC. 12508 -mno-id-shared-library 12509 Generate code that doesn't assume ID-based shared libraries are being used. This is the default. 12510 -mshared-library-id=n 12511 Specifies the identification number of the ID-based shared library being compiled. Specifying a value of 0 12512 generates more compact code; specifying other values forces the allocation of that number to the current 12513 library, but is no more space- or time-efficient than omitting this option. 12514 -mxgot 12515 -mno-xgot 12516 When generating position-independent code for ColdFire, generate code that works if the GOT has more than 12517 8192 entries. This code is larger and slower than code generated without this option. On M680x0 12518 processors, this option is not needed; -fPIC suffices. 12519 GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it 12520 only works if the GOT is smaller than about 64k. Anything larger causes the linker to report an error such 12521 as: 12522 relocation truncated to fit: R_68K_GOT16O foobar 12523 If this happens, you should recompile your code with -mxgot. It should then work with very large GOTs. 12524 However, code generated with -mxgot is less efficient, since it takes 4 instructions to fetch the value of 12525 a global symbol. 12526 Note that some linkers, including newer versions of the GNU linker, can create multiple GOTs and sort GOT 12527 entries. If you have such a linker, you should only need to use -mxgot when compiling a single object file 12528 that accesses more than 8192 GOT entries. Very few do. 12529 These options have no effect unless GCC is generating position-independent code. 12530 -mlong-jump-table-offsets 12531 Use 32-bit offsets in "switch" tables. The default is to use 16-bit offsets. 12532 MCore Options 12533 These are the -m options defined for the Motorola M*Core processors. 12534 -mhardlit 12535 -mno-hardlit 12536 Inline constants into the code stream if it can be done in two instructions or less. 12537 -mdiv 12538 -mno-div 12539 Use the divide instruction. (Enabled by default). 12540 -mrelax-immediate 12541 -mno-relax-immediate 12542 Allow arbitrary-sized immediates in bit operations. 12543 -mwide-bitfields 12544 -mno-wide-bitfields 12545 Always treat bit-fields as "int"-sized. 12546 -m4byte-functions 12547 -mno-4byte-functions 12548 Force all functions to be aligned to a 4-byte boundary. 12549 -mcallgraph-data 12550 -mno-callgraph-data 12551 Emit callgraph information. 12552 -mslow-bytes 12553 -mno-slow-bytes 12554 Prefer word access when reading byte quantities. 12555 -mlittle-endian 12556 -mbig-endian 12557 Generate code for a little-endian target. 12558 -m210 12559 -m340 12560 Generate code for the 210 processor. 12561 -mno-lsim 12562 Assume that runtime support has been provided and so omit the simulator library (libsim.a) from the linker 12563 command line. 12564 -mstack-increment=size 12565 Set the maximum amount for a single stack increment operation. Large values can increase the speed of 12566 programs that contain functions that need a large amount of stack space, but they can also trigger a 12567 segmentation fault if the stack is extended too much. The default value is 0x1000. 12568 MeP Options 12569 -mabsdiff 12570 Enables the "abs" instruction, which is the absolute difference between two registers. 12571 -mall-opts 12572 Enables all the optional instructions---average, multiply, divide, bit operations, leading zero, absolute 12573 difference, min/max, clip, and saturation. 12574 -maverage 12575 Enables the "ave" instruction, which computes the average of two registers. 12576 -mbased=n 12577 Variables of size n bytes or smaller are placed in the ".based" section by default. Based variables use 12578 the $tp register as a base register, and there is a 128-byte limit to the ".based" section. 12579 -mbitops 12580 Enables the bit operation instructions---bit test ("btstm"), set ("bsetm"), clear ("bclrm"), invert 12581 ("bnotm"), and test-and-set ("tas"). 12582 -mc=name 12583 Selects which section constant data is placed in. name may be tiny, near, or far. 12584 -mclip 12585 Enables the "clip" instruction. Note that -mclip is not useful unless you also provide -mminmax. 12586 -mconfig=name 12587 Selects one of the built-in core configurations. Each MeP chip has one or more modules in it; each module 12588 has a core CPU and a variety of coprocessors, optional instructions, and peripherals. The "MeP-Integrator" 12589 tool, not part of GCC, provides these configurations through this option; using this option is the same as 12590 using all the corresponding command-line options. The default configuration is default. 12591 -mcop 12592 Enables the coprocessor instructions. By default, this is a 32-bit coprocessor. Note that the coprocessor 12593 is normally enabled via the -mconfig= option. 12594 -mcop32 12595 Enables the 32-bit coprocessor's instructions. 12596 -mcop64 12597 Enables the 64-bit coprocessor's instructions. 12598 -mivc2 12599 Enables IVC2 scheduling. IVC2 is a 64-bit VLIW coprocessor. 12600 -mdc 12601 Causes constant variables to be placed in the ".near" section. 12602 -mdiv 12603 Enables the "div" and "divu" instructions. 12604 -meb 12605 Generate big-endian code. 12606 -mel 12607 Generate little-endian code. 12608 -mio-volatile 12609 Tells the compiler that any variable marked with the "io" attribute is to be considered volatile. 12610 -ml Causes variables to be assigned to the ".far" section by default. 12611 -mleadz 12612 Enables the "leadz" (leading zero) instruction. 12613 -mm Causes variables to be assigned to the ".near" section by default. 12614 -mminmax 12615 Enables the "min" and "max" instructions. 12616 -mmult 12617 Enables the multiplication and multiply-accumulate instructions. 12618 -mno-opts 12619 Disables all the optional instructions enabled by -mall-opts. 12620 -mrepeat 12621 Enables the "repeat" and "erepeat" instructions, used for low-overhead looping. 12622 -ms Causes all variables to default to the ".tiny" section. Note that there is a 65536-byte limit to this 12623 section. Accesses to these variables use the %gp base register. 12624 -msatur 12625 Enables the saturation instructions. Note that the compiler does not currently generate these itself, but 12626 this option is included for compatibility with other tools, like "as". 12627 -msdram 12628 Link the SDRAM-based runtime instead of the default ROM-based runtime. 12629 -msim 12630 Link the simulator run-time libraries. 12631 -msimnovec 12632 Link the simulator runtime libraries, excluding built-in support for reset and exception vectors and 12633 tables. 12634 -mtf 12635 Causes all functions to default to the ".far" section. Without this option, functions default to the 12636 ".near" section. 12637 -mtiny=n 12638 Variables that are n bytes or smaller are allocated to the ".tiny" section. These variables use the $gp 12639 base register. The default for this option is 4, but note that there's a 65536-byte limit to the ".tiny" 12640 section. 12641 MicroBlaze Options 12642 -msoft-float 12643 Use software emulation for floating point (default). 12644 -mhard-float 12645 Use hardware floating-point instructions. 12646 -mmemcpy 12647 Do not optimize block moves, use "memcpy". 12648 -mno-clearbss 12649 This option is deprecated. Use -fno-zero-initialized-in-bss instead. 12650 -mcpu=cpu-type 12651 Use features of, and schedule code for, the given CPU. Supported values are in the format vX.YY.Z, where X 12652 is a major version, YY is the minor version, and Z is compatibility code. Example values are v3.00.a, 12653 v4.00.b, v5.00.a, v5.00.b, v6.00.a. 12654 -mxl-soft-mul 12655 Use software multiply emulation (default). 12656 -mxl-soft-div 12657 Use software emulation for divides (default). 12658 -mxl-barrel-shift 12659 Use the hardware barrel shifter. 12660 -mxl-pattern-compare 12661 Use pattern compare instructions. 12662 -msmall-divides 12663 Use table lookup optimization for small signed integer divisions. 12664 -mxl-stack-check 12665 This option is deprecated. Use -fstack-check instead. 12666 -mxl-gp-opt 12667 Use GP-relative ".sdata"/".sbss" sections. 12668 -mxl-multiply-high 12669 Use multiply high instructions for high part of 32x32 multiply. 12670 -mxl-float-convert 12671 Use hardware floating-point conversion instructions. 12672 -mxl-float-sqrt 12673 Use hardware floating-point square root instruction. 12674 -mbig-endian 12675 Generate code for a big-endian target. 12676 -mlittle-endian 12677 Generate code for a little-endian target. 12678 -mxl-reorder 12679 Use reorder instructions (swap and byte reversed load/store). 12680 -mxl-mode-app-model 12681 Select application model app-model. Valid models are 12682 executable 12683 normal executable (default), uses startup code crt0.o. 12684 -mpic-data-is-text-relative 12685 Assume that the displacement between the text and data segments is fixed at static link time. This 12686 allows data to be referenced by offset from start of text address instead of GOT since PC-relative 12687 addressing is not supported. 12688 xmdstub 12689 for use with Xilinx Microprocessor Debugger (XMD) based software intrusive debug agent called xmdstub. 12690 This uses startup file crt1.o and sets the start address of the program to 0x800. 12691 bootstrap 12692 for applications that are loaded using a bootloader. This model uses startup file crt2.o which does 12693 not contain a processor reset vector handler. This is suitable for transferring control on a processor 12694 reset to the bootloader rather than the application. 12695 novectors 12696 for applications that do not require any of the MicroBlaze vectors. This option may be useful for 12697 applications running within a monitoring application. This model uses crt3.o as a startup file. 12698 Option -xl-mode-app-model is a deprecated alias for -mxl-mode-app-model. 12699 MIPS Options 12700 -EB Generate big-endian code. 12701 -EL Generate little-endian code. This is the default for mips*el-*-* configurations. 12702 -march=arch 12703 Generate code that runs on arch, which can be the name of a generic MIPS ISA, or the name of a particular 12704 processor. The ISA names are: mips1, mips2, mips3, mips4, mips32, mips32r2, mips32r3, mips32r5, mips32r6, 12705 mips64, mips64r2, mips64r3, mips64r5 and mips64r6. The processor names are: 4kc, 4km, 4kp, 4ksc, 4kec, 12706 4kem, 4kep, 4ksd, 5kc, 5kf, 20kc, 24kc, 24kf2_1, 24kf1_1, 24kec, 24kef2_1, 24kef1_1, 34kc, 34kf2_1, 12707 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf1_1, i6400, i6500, interaptiv, 12708 loongson2e, loongson2f, loongson3a, gs464, gs464e, gs264e, m4k, m14k, m14kc, m14ke, m14kec, m5100, m5101, 12709 octeon, octeon , octeon2, octeon3, orion, p5600, p6600, r2000, r3000, r3900, r4000, r4400, r4600, r4650, 12710 r4700, r5900, r6000, r8000, rm7000, rm9000, r10000, r12000, r14000, r16000, sb1, sr71000, vr4100, vr4111, 12711 vr4120, vr4130, vr4300, vr5000, vr5400, vr5500, xlr and xlp. The special value from-abi selects the most 12712 compatible architecture for the selected ABI (that is, mips1 for 32-bit ABIs and mips3 for 64-bit ABIs). 12713 The native Linux/GNU toolchain also supports the value native, which selects the best architecture option 12714 for the host processor. -march=native has no effect if GCC does not recognize the processor. 12715 In processor names, a final 000 can be abbreviated as k (for example, -march=r2k). Prefixes are optional, 12716 and vr may be written r. 12717 Names of the form nf2_1 refer to processors with FPUs clocked at half the rate of the core, names of the 12718 form nf1_1 refer to processors with FPUs clocked at the same rate as the core, and names of the form nf3_2 12719 refer to processors with FPUs clocked a ratio of 3:2 with respect to the core. For compatibility reasons, 12720 nf is accepted as a synonym for nf2_1 while nx and bfx are accepted as synonyms for nf1_1. 12721 GCC defines two macros based on the value of this option. The first is "_MIPS_ARCH", which gives the name 12722 of target architecture, as a string. The second has the form "_MIPS_ARCH_foo", where foo is the 12723 capitalized value of "_MIPS_ARCH". For example, -march=r2000 sets "_MIPS_ARCH" to "r2000" and defines the 12724 macro "_MIPS_ARCH_R2000". 12725 Note that the "_MIPS_ARCH" macro uses the processor names given above. In other words, it has the full 12726 prefix and does not abbreviate 000 as k. In the case of from-abi, the macro names the resolved 12727 architecture (either "mips1" or "mips3"). It names the default architecture when no -march option is 12728 given. 12729 -mtune=arch 12730 Optimize for arch. Among other things, this option controls the way instructions are scheduled, and the 12731 perceived cost of arithmetic operations. The list of arch values is the same as for -march. 12732 When this option is not used, GCC optimizes for the processor specified by -march. By using -march and 12733 -mtune together, it is possible to generate code that runs on a family of processors, but optimize the code 12734 for one particular member of that family. 12735 -mtune defines the macros "_MIPS_TUNE" and "_MIPS_TUNE_foo", which work in the same way as the -march ones 12736 described above. 12737 -mips1 12738 Equivalent to -march=mips1. 12739 -mips2 12740 Equivalent to -march=mips2. 12741 -mips3 12742 Equivalent to -march=mips3. 12743 -mips4 12744 Equivalent to -march=mips4. 12745 -mips32 12746 Equivalent to -march=mips32. 12747 -mips32r3 12748 Equivalent to -march=mips32r3. 12749 -mips32r5 12750 Equivalent to -march=mips32r5. 12751 -mips32r6 12752 Equivalent to -march=mips32r6. 12753 -mips64 12754 Equivalent to -march=mips64. 12755 -mips64r2 12756 Equivalent to -march=mips64r2. 12757 -mips64r3 12758 Equivalent to -march=mips64r3. 12759 -mips64r5 12760 Equivalent to -march=mips64r5. 12761 -mips64r6 12762 Equivalent to -march=mips64r6. 12763 -mips16 12764 -mno-mips16 12765 Generate (do not generate) MIPS16 code. If GCC is targeting a MIPS32 or MIPS64 architecture, it makes use 12766 of the MIPS16e ASE. 12767 MIPS16 code generation can also be controlled on a per-function basis by means of "mips16" and "nomips16" 12768 attributes. 12769 -mflip-mips16 12770 Generate MIPS16 code on alternating functions. This option is provided for regression testing of mixed 12771 MIPS16/non-MIPS16 code generation, and is not intended for ordinary use in compiling user code. 12772 -minterlink-compressed 12773 -mno-interlink-compressed 12774 Require (do not require) that code using the standard (uncompressed) MIPS ISA be link-compatible with 12775 MIPS16 and microMIPS code, and vice versa. 12776 For example, code using the standard ISA encoding cannot jump directly to MIPS16 or microMIPS code; it must 12777 either use a call or an indirect jump. -minterlink-compressed therefore disables direct jumps unless GCC 12778 knows that the target of the jump is not compressed. 12779 -minterlink-mips16 12780 -mno-interlink-mips16 12781 Aliases of -minterlink-compressed and -mno-interlink-compressed. These options predate the microMIPS ASE 12782 and are retained for backwards compatibility. 12783 -mabi=32 12784 -mabi=o64 12785 -mabi=n32 12786 -mabi=64 12787 -mabi=eabi 12788 Generate code for the given ABI. 12789 Note that the EABI has a 32-bit and a 64-bit variant. GCC normally generates 64-bit code when you select a 12790 64-bit architecture, but you can use -mgp32 to get 32-bit code instead. 12791 For information about the O64 ABI, see <http://gcc.gnu.org/projects/mipso64-abi.html>. 12792 GCC supports a variant of the o32 ABI in which floating-point registers are 64 rather than 32 bits wide. 12793 You can select this combination with -mabi=32 -mfp64. This ABI relies on the "mthc1" and "mfhc1" 12794 instructions and is therefore only supported for MIPS32R2, MIPS32R3 and MIPS32R5 processors. 12795 The register assignments for arguments and return values remain the same, but each scalar value is passed 12796 in a single 64-bit register rather than a pair of 32-bit registers. For example, scalar floating-point 12797 values are returned in $f0 only, not a $f0/$f1 pair. The set of call-saved registers also remains the same 12798 in that the even-numbered double-precision registers are saved. 12799 Two additional variants of the o32 ABI are supported to enable a transition from 32-bit to 64-bit 12800 registers. These are FPXX (-mfpxx) and FP64A (-mfp64 -mno-odd-spreg). The FPXX extension mandates that 12801 all code must execute correctly when run using 32-bit or 64-bit registers. The code can be interlinked 12802 with either FP32 or FP64, but not both. The FP64A extension is similar to the FP64 extension but forbids 12803 the use of odd-numbered single-precision registers. This can be used in conjunction with the "FRE" mode of 12804 FPUs in MIPS32R5 processors and allows both FP32 and FP64A code to interlink and run in the same process 12805 without changing FPU modes. 12806 -mabicalls 12807 -mno-abicalls 12808 Generate (do not generate) code that is suitable for SVR4-style dynamic objects. -mabicalls is the default 12809 for SVR4-based systems. 12810 -mshared 12811 -mno-shared 12812 Generate (do not generate) code that is fully position-independent, and that can therefore be linked into 12813 shared libraries. This option only affects -mabicalls. 12814 All -mabicalls code has traditionally been position-independent, regardless of options like -fPIC and 12815 -fpic. However, as an extension, the GNU toolchain allows executables to use absolute accesses for 12816 locally-binding symbols. It can also use shorter GP initialization sequences and generate direct calls to 12817 locally-defined functions. This mode is selected by -mno-shared. 12818 -mno-shared depends on binutils 2.16 or higher and generates objects that can only be linked by the GNU 12819 linker. However, the option does not affect the ABI of the final executable; it only affects the ABI of 12820 relocatable objects. Using -mno-shared generally makes executables both smaller and quicker. 12821 -mshared is the default. 12822 -mplt 12823 -mno-plt 12824 Assume (do not assume) that the static and dynamic linkers support PLTs and copy relocations. This option 12825 only affects -mno-shared -mabicalls. For the n64 ABI, this option has no effect without -msym32. 12826 You can make -mplt the default by configuring GCC with --with-mips-plt. The default is -mno-plt otherwise. 12827 -mxgot 12828 -mno-xgot 12829 Lift (do not lift) the usual restrictions on the size of the global offset table. 12830 GCC normally uses a single instruction to load values from the GOT. While this is relatively efficient, it 12831 only works if the GOT is smaller than about 64k. Anything larger causes the linker to report an error such 12832 as: 12833 relocation truncated to fit: R_MIPS_GOT16 foobar 12834 If this happens, you should recompile your code with -mxgot. This works with very large GOTs, although the 12835 code is also less efficient, since it takes three instructions to fetch the value of a global symbol. 12836 Note that some linkers can create multiple GOTs. If you have such a linker, you should only need to use 12837 -mxgot when a single object file accesses more than 64k's worth of GOT entries. Very few do. 12838 These options have no effect unless GCC is generating position independent code. 12839 -mgp32 12840 Assume that general-purpose registers are 32 bits wide. 12841 -mgp64 12842 Assume that general-purpose registers are 64 bits wide. 12843 -mfp32 12844 Assume that floating-point registers are 32 bits wide. 12845 -mfp64 12846 Assume that floating-point registers are 64 bits wide. 12847 -mfpxx 12848 Do not assume the width of floating-point registers. 12849 -mhard-float 12850 Use floating-point coprocessor instructions. 12851 -msoft-float 12852 Do not use floating-point coprocessor instructions. Implement floating-point calculations using library 12853 calls instead. 12854 -mno-float 12855 Equivalent to -msoft-float, but additionally asserts that the program being compiled does not perform any 12856 floating-point operations. This option is presently supported only by some bare-metal MIPS configurations, 12857 where it may select a special set of libraries that lack all floating-point support (including, for 12858 example, the floating-point "printf" formats). If code compiled with -mno-float accidentally contains 12859 floating-point operations, it is likely to suffer a link-time or run-time failure. 12860 -msingle-float 12861 Assume that the floating-point coprocessor only supports single-precision operations. 12862 -mdouble-float 12863 Assume that the floating-point coprocessor supports double-precision operations. This is the default. 12864 -modd-spreg 12865 -mno-odd-spreg 12866 Enable the use of odd-numbered single-precision floating-point registers for the o32 ABI. This is the 12867 default for processors that are known to support these registers. When using the o32 FPXX ABI, 12868 -mno-odd-spreg is set by default. 12869 -mabs=2008 12870 -mabs=legacy 12871 These options control the treatment of the special not-a-number (NaN) IEEE 754 floating-point data with the 12872 "abs.fmt" and "neg.fmt" machine instructions. 12873 By default or when -mabs=legacy is used the legacy treatment is selected. In this case these instructions 12874 are considered arithmetic and avoided where correct operation is required and the input operand might be a 12875 NaN. A longer sequence of instructions that manipulate the sign bit of floating-point datum manually is 12876 used instead unless the -ffinite-math-only option has also been specified. 12877 The -mabs=2008 option selects the IEEE 754-2008 treatment. In this case these instructions are considered 12878 non-arithmetic and therefore operating correctly in all cases, including in particular where the input 12879 operand is a NaN. These instructions are therefore always used for the respective operations. 12880 -mnan=2008 12881 -mnan=legacy 12882 These options control the encoding of the special not-a-number (NaN) IEEE 754 floating-point data. 12883 The -mnan=legacy option selects the legacy encoding. In this case quiet NaNs (qNaNs) are denoted by the 12884 first bit of their trailing significand field being 0, whereas signaling NaNs (sNaNs) are denoted by the 12885 first bit of their trailing significand field being 1. 12886 The -mnan=2008 option selects the IEEE 754-2008 encoding. In this case qNaNs are denoted by the first bit 12887 of their trailing significand field being 1, whereas sNaNs are denoted by the first bit of their trailing 12888 significand field being 0. 12889 The default is -mnan=legacy unless GCC has been configured with --with-nan=2008. 12890 -mllsc 12891 -mno-llsc 12892 Use (do not use) ll, sc, and sync instructions to implement atomic memory built-in functions. When neither 12893 option is specified, GCC uses the instructions if the target architecture supports them. 12894 -mllsc is useful if the runtime environment can emulate the instructions and -mno-llsc can be useful when 12895 compiling for nonstandard ISAs. You can make either option the default by configuring GCC with --with-llsc 12896 and --without-llsc respectively. --with-llsc is the default for some configurations; see the installation 12897 documentation for details. 12898 -mdsp 12899 -mno-dsp 12900 Use (do not use) revision 1 of the MIPS DSP ASE. 12901 This option defines the preprocessor macro "__mips_dsp". It also defines "__mips_dsp_rev" to 1. 12902 -mdspr2 12903 -mno-dspr2 12904 Use (do not use) revision 2 of the MIPS DSP ASE. 12905 This option defines the preprocessor macros "__mips_dsp" and "__mips_dspr2". It also defines 12906 "__mips_dsp_rev" to 2. 12907 -msmartmips 12908 -mno-smartmips 12909 Use (do not use) the MIPS SmartMIPS ASE. 12910 -mpaired-single 12911 -mno-paired-single 12912 Use (do not use) paired-single floating-point instructions. 12913 This option requires hardware floating-point support to be enabled. 12914 -mdmx 12915 -mno-mdmx 12916 Use (do not use) MIPS Digital Media Extension instructions. This option can only be used when generating 12917 64-bit code and requires hardware floating-point support to be enabled. 12918 -mips3d 12919 -mno-mips3d 12920 Use (do not use) the MIPS-3D ASE. The option -mips3d implies -mpaired-single. 12921 -mmicromips 12922 -mno-micromips 12923 Generate (do not generate) microMIPS code. 12924 MicroMIPS code generation can also be controlled on a per-function basis by means of "micromips" and 12925 "nomicromips" attributes. 12926 -mmt 12927 -mno-mt 12928 Use (do not use) MT Multithreading instructions. 12929 -mmcu 12930 -mno-mcu 12931 Use (do not use) the MIPS MCU ASE instructions. 12932 -meva 12933 -mno-eva 12934 Use (do not use) the MIPS Enhanced Virtual Addressing instructions. 12935 -mvirt 12936 -mno-virt 12937 Use (do not use) the MIPS Virtualization (VZ) instructions. 12938 -mxpa 12939 -mno-xpa 12940 Use (do not use) the MIPS eXtended Physical Address (XPA) instructions. 12941 -mcrc 12942 -mno-crc 12943 Use (do not use) the MIPS Cyclic Redundancy Check (CRC) instructions. 12944 -mginv 12945 -mno-ginv 12946 Use (do not use) the MIPS Global INValidate (GINV) instructions. 12947 -mloongson-mmi 12948 -mno-loongson-mmi 12949 Use (do not use) the MIPS Loongson MultiMedia extensions Instructions (MMI). 12950 -mloongson-ext 12951 -mno-loongson-ext 12952 Use (do not use) the MIPS Loongson EXTensions (EXT) instructions. 12953 -mloongson-ext2 12954 -mno-loongson-ext2 12955 Use (do not use) the MIPS Loongson EXTensions r2 (EXT2) instructions. 12956 -mlong64 12957 Force "long" types to be 64 bits wide. See -mlong32 for an explanation of the default and the way that the 12958 pointer size is determined. 12959 -mlong32 12960 Force "long", "int", and pointer types to be 32 bits wide. 12961 The default size of "int"s, "long"s and pointers depends on the ABI. All the supported ABIs use 32-bit 12962 "int"s. The n64 ABI uses 64-bit "long"s, as does the 64-bit EABI; the others use 32-bit "long"s. Pointers 12963 are the same size as "long"s, or the same size as integer registers, whichever is smaller. 12964 -msym32 12965 -mno-sym32 12966 Assume (do not assume) that all symbols have 32-bit values, regardless of the selected ABI. This option is 12967 useful in combination with -mabi=64 and -mno-abicalls because it allows GCC to generate shorter and faster 12968 references to symbolic addresses. 12969 -G num 12970 Put definitions of externally-visible data in a small data section if that data is no bigger than num 12971 bytes. GCC can then generate more efficient accesses to the data; see -mgpopt for details. 12972 The default -G option depends on the configuration. 12973 -mlocal-sdata 12974 -mno-local-sdata 12975 Extend (do not extend) the -G behavior to local data too, such as to static variables in C. -mlocal-sdata 12976 is the default for all configurations. 12977 If the linker complains that an application is using too much small data, you might want to try rebuilding 12978 the less performance-critical parts with -mno-local-sdata. You might also want to build large libraries 12979 with -mno-local-sdata, so that the libraries leave more room for the main program. 12980 -mextern-sdata 12981 -mno-extern-sdata 12982 Assume (do not assume) that externally-defined data is in a small data section if the size of that data is 12983 within the -G limit. -mextern-sdata is the default for all configurations. 12984 If you compile a module Mod with -mextern-sdata -G num -mgpopt, and Mod references a variable Var that is 12985 no bigger than num bytes, you must make sure that Var is placed in a small data section. If Var is defined 12986 by another module, you must either compile that module with a high-enough -G setting or attach a "section" 12987 attribute to Var's definition. If Var is common, you must link the application with a high-enough -G 12988 setting. 12989 The easiest way of satisfying these restrictions is to compile and link every module with the same -G 12990 option. However, you may wish to build a library that supports several different small data limits. You 12991 can do this by compiling the library with the highest supported -G setting and additionally using 12992 -mno-extern-sdata to stop the library from making assumptions about externally-defined data. 12993 -mgpopt 12994 -mno-gpopt 12995 Use (do not use) GP-relative accesses for symbols that are known to be in a small data section; see -G, 12996 -mlocal-sdata and -mextern-sdata. -mgpopt is the default for all configurations. 12997 -mno-gpopt is useful for cases where the $gp register might not hold the value of "_gp". For example, if 12998 the code is part of a library that might be used in a boot monitor, programs that call boot monitor 12999 routines pass an unknown value in $gp. (In such situations, the boot monitor itself is usually compiled 13000 with -G0.) 13001 -mno-gpopt implies -mno-local-sdata and -mno-extern-sdata. 13002 -membedded-data 13003 -mno-embedded-data 13004 Allocate variables to the read-only data section first if possible, then next in the small data section if 13005 possible, otherwise in data. This gives slightly slower code than the default, but reduces the amount of 13006 RAM required when executing, and thus may be preferred for some embedded systems. 13007 -muninit-const-in-rodata 13008 -mno-uninit-const-in-rodata 13009 Put uninitialized "const" variables in the read-only data section. This option is only meaningful in 13010 conjunction with -membedded-data. 13011 -mcode-readable=setting 13012 Specify whether GCC may generate code that reads from executable sections. There are three possible 13013 settings: 13014 -mcode-readable=yes 13015 Instructions may freely access executable sections. This is the default setting. 13016 -mcode-readable=pcrel 13017 MIPS16 PC-relative load instructions can access executable sections, but other instructions must not do 13018 so. This option is useful on 4KSc and 4KSd processors when the code TLBs have the Read Inhibit bit 13019 set. It is also useful on processors that can be configured to have a dual instruction/data SRAM 13020 interface and that, like the M4K, automatically redirect PC-relative loads to the instruction RAM. 13021 -mcode-readable=no 13022 Instructions must not access executable sections. This option can be useful on targets that are 13023 configured to have a dual instruction/data SRAM interface but that (unlike the M4K) do not 13024 automatically redirect PC-relative loads to the instruction RAM. 13025 -msplit-addresses 13026 -mno-split-addresses 13027 Enable (disable) use of the "%hi()" and "%lo()" assembler relocation operators. This option has been 13028 superseded by -mexplicit-relocs but is retained for backwards compatibility. 13029 -mexplicit-relocs 13030 -mno-explicit-relocs 13031 Use (do not use) assembler relocation operators when dealing with symbolic addresses. The alternative, 13032 selected by -mno-explicit-relocs, is to use assembler macros instead. 13033 -mexplicit-relocs is the default if GCC was configured to use an assembler that supports relocation 13034 operators. 13035 -mcheck-zero-division 13036 -mno-check-zero-division 13037 Trap (do not trap) on integer division by zero. 13038 The default is -mcheck-zero-division. 13039 -mdivide-traps 13040 -mdivide-breaks 13041 MIPS systems check for division by zero by generating either a conditional trap or a break instruction. 13042 Using traps results in smaller code, but is only supported on MIPS II and later. Also, some versions of 13043 the Linux kernel have a bug that prevents trap from generating the proper signal ("SIGFPE"). Use 13044 -mdivide-traps to allow conditional traps on architectures that support them and -mdivide-breaks to force 13045 the use of breaks. 13046 The default is usually -mdivide-traps, but this can be overridden at configure time using 13047 --with-divide=breaks. Divide-by-zero checks can be completely disabled using -mno-check-zero-division. 13048 -mload-store-pairs 13049 -mno-load-store-pairs 13050 Enable (disable) an optimization that pairs consecutive load or store instructions to enable load/store 13051 bonding. This option is enabled by default but only takes effect when the selected architecture is known 13052 to support bonding. 13053 -mmemcpy 13054 -mno-memcpy 13055 Force (do not force) the use of "memcpy" for non-trivial block moves. The default is -mno-memcpy, which 13056 allows GCC to inline most constant-sized copies. 13057 -mlong-calls 13058 -mno-long-calls 13059 Disable (do not disable) use of the "jal" instruction. Calling functions using "jal" is more efficient but 13060 requires the caller and callee to be in the same 256 megabyte segment. 13061 This option has no effect on abicalls code. The default is -mno-long-calls. 13062 -mmad 13063 -mno-mad 13064 Enable (disable) use of the "mad", "madu" and "mul" instructions, as provided by the R4650 ISA. 13065 -mimadd 13066 -mno-imadd 13067 Enable (disable) use of the "madd" and "msub" integer instructions. The default is -mimadd on 13068 architectures that support "madd" and "msub" except for the 74k architecture where it was found to generate 13069 slower code. 13070 -mfused-madd 13071 -mno-fused-madd 13072 Enable (disable) use of the floating-point multiply-accumulate instructions, when they are available. The 13073 default is -mfused-madd. 13074 On the R8000 CPU when multiply-accumulate instructions are used, the intermediate product is calculated to 13075 infinite precision and is not subject to the FCSR Flush to Zero bit. This may be undesirable in some 13076 circumstances. On other processors the result is numerically identical to the equivalent computation using 13077 separate multiply, add, subtract and negate instructions. 13078 -nocpp 13079 Tell the MIPS assembler to not run its preprocessor over user assembler files (with a .s suffix) when 13080 assembling them. 13081 -mfix-24k 13082 -mno-fix-24k 13083 Work around the 24K E48 (lost data on stores during refill) errata. The workarounds are implemented by the 13084 assembler rather than by GCC. 13085 -mfix-r4000 13086 -mno-fix-r4000 13087 Work around certain R4000 CPU errata: 13088 - A double-word or a variable shift may give an incorrect result if executed immediately after starting 13089 an integer division. 13090 - A double-word or a variable shift may give an incorrect result if executed while an integer 13091 multiplication is in progress. 13092 - An integer division may give an incorrect result if started in a delay slot of a taken branch or a 13093 jump. 13094 -mfix-r4400 13095 -mno-fix-r4400 13096 Work around certain R4400 CPU errata: 13097 - A double-word or a variable shift may give an incorrect result if executed immediately after starting 13098 an integer division. 13099 -mfix-r10000 13100 -mno-fix-r10000 13101 Work around certain R10000 errata: 13102 - "ll"/"sc" sequences may not behave atomically on revisions prior to 3.0. They may deadlock on 13103 revisions 2.6 and earlier. 13104 This option can only be used if the target architecture supports branch-likely instructions. -mfix-r10000 13105 is the default when -march=r10000 is used; -mno-fix-r10000 is the default otherwise. 13106 -mfix-r5900 13107 -mno-fix-r5900 13108 Do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at 13109 the end of a short loop of six instructions or fewer and always schedule a "nop" instruction there instead. 13110 The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware 13111 bug in the R5900 chip. The workaround is implemented by the assembler rather than by GCC. 13112 -mfix-rm7000 13113 -mno-fix-rm7000 13114 Work around the RM7000 "dmult"/"dmultu" errata. The workarounds are implemented by the assembler rather 13115 than by GCC. 13116 -mfix-vr4120 13117 -mno-fix-vr4120 13118 Work around certain VR4120 errata: 13119 - "dmultu" does not always produce the correct result. 13120 - "div" and "ddiv" do not always produce the correct result if one of the operands is negative. 13121 The workarounds for the division errata rely on special functions in libgcc.a. At present, these functions 13122 are only provided by the "mips64vr*-elf" configurations. 13123 Other VR4120 errata require a NOP to be inserted between certain pairs of instructions. These errata are 13124 handled by the assembler, not by GCC itself. 13125 -mfix-vr4130 13126 Work around the VR4130 "mflo"/"mfhi" errata. The workarounds are implemented by the assembler rather than 13127 by GCC, although GCC avoids using "mflo" and "mfhi" if the VR4130 "macc", "macchi", "dmacc" and "dmacchi" 13128 instructions are available instead. 13129 -mfix-sb1 13130 -mno-fix-sb1 13131 Work around certain SB-1 CPU core errata. (This flag currently works around the SB-1 revision 2 "F1" and 13132 "F2" floating-point errata.) 13133 -mr10k-cache-barrier=setting 13134 Specify whether GCC should insert cache barriers to avoid the side effects of speculation on R10K 13135 processors. 13136 In common with many processors, the R10K tries to predict the outcome of a conditional branch and 13137 speculatively executes instructions from the "taken" branch. It later aborts these instructions if the 13138 predicted outcome is wrong. However, on the R10K, even aborted instructions can have side effects. 13139 This problem only affects kernel stores and, depending on the system, kernel loads. As an example, a 13140 speculatively-executed store may load the target memory into cache and mark the cache line as dirty, even 13141 if the store itself is later aborted. If a DMA operation writes to the same area of memory before the 13142 "dirty" line is flushed, the cached data overwrites the DMA-ed data. See the R10K processor manual for a 13143 full description, including other potential problems. 13144 One workaround is to insert cache barrier instructions before every memory access that might be 13145 speculatively executed and that might have side effects even if aborted. -mr10k-cache-barrier=setting 13146 controls GCC's implementation of this workaround. It assumes that aborted accesses to any byte in the 13147 following regions does not have side effects: 13148 1. the memory occupied by the current function's stack frame; 13149 2. the memory occupied by an incoming stack argument; 13150 3. the memory occupied by an object with a link-time-constant address. 13151 It is the kernel's responsibility to ensure that speculative accesses to these regions are indeed safe. 13152 If the input program contains a function declaration such as: 13153 void foo (void); 13154 then the implementation of "foo" must allow "j foo" and "jal foo" to be executed speculatively. GCC honors 13155 this restriction for functions it compiles itself. It expects non-GCC functions (such as hand-written 13156 assembly code) to do the same. 13157 The option has three forms: 13158 -mr10k-cache-barrier=load-store 13159 Insert a cache barrier before a load or store that might be speculatively executed and that might have 13160 side effects even if aborted. 13161 -mr10k-cache-barrier=store 13162 Insert a cache barrier before a store that might be speculatively executed and that might have side 13163 effects even if aborted. 13164 -mr10k-cache-barrier=none 13165 Disable the insertion of cache barriers. This is the default setting. 13166 -mflush-func=func 13167 -mno-flush-func 13168 Specifies the function to call to flush the I and D caches, or to not call any such function. If called, 13169 the function must take the same arguments as the common "_flush_func", that is, the address of the memory 13170 range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both 13171 caches). The default depends on the target GCC was configured for, but commonly is either "_flush_func" or 13172 "__cpu_flush". 13173 mbranch-cost=num 13174 Set the cost of branches to roughly num "simple" instructions. This cost is only a heuristic and is not 13175 guaranteed to produce consistent results across releases. A zero cost redundantly selects the default, 13176 which is based on the -mtune setting. 13177 -mbranch-likely 13178 -mno-branch-likely 13179 Enable or disable use of Branch Likely instructions, regardless of the default for the selected 13180 architecture. By default, Branch Likely instructions may be generated if they are supported by the 13181 selected architecture. An exception is for the MIPS32 and MIPS64 architectures and processors that 13182 implement those architectures; for those, Branch Likely instructions are not be generated by default 13183 because the MIPS32 and MIPS64 architectures specifically deprecate their use. 13184 -mcompact-branches=never 13185 -mcompact-branches=optimal 13186 -mcompact-branches=always 13187 These options control which form of branches will be generated. The default is -mcompact-branches=optimal. 13188 The -mcompact-branches=never option ensures that compact branch instructions will never be generated. 13189 The -mcompact-branches=always option ensures that a compact branch instruction will be generated if 13190 available. If a compact branch instruction is not available, a delay slot form of the branch will be used 13191 instead. 13192 This option is supported from MIPS Release 6 onwards. 13193 The -mcompact-branches=optimal option will cause a delay slot branch to be used if one is available in the 13194 current ISA and the delay slot is successfully filled. If the delay slot is not filled, a compact branch 13195 will be chosen if one is available. 13196 -mfp-exceptions 13197 -mno-fp-exceptions 13198 Specifies whether FP exceptions are enabled. This affects how FP instructions are scheduled for some 13199 processors. The default is that FP exceptions are enabled. 13200 For instance, on the SB-1, if FP exceptions are disabled, and we are emitting 64-bit code, then we can use 13201 both FP pipes. Otherwise, we can only use one FP pipe. 13202 -mvr4130-align 13203 -mno-vr4130-align 13204 The VR4130 pipeline is two-way superscalar, but can only issue two instructions together if the first one 13205 is 8-byte aligned. When this option is enabled, GCC aligns pairs of instructions that it thinks should 13206 execute in parallel. 13207 This option only has an effect when optimizing for the VR4130. It normally makes code faster, but at the 13208 expense of making it bigger. It is enabled by default at optimization level -O3. 13209 -msynci 13210 -mno-synci 13211 Enable (disable) generation of "synci" instructions on architectures that support it. The "synci" 13212 instructions (if enabled) are generated when "__builtin___clear_cache" is compiled. 13213 This option defaults to -mno-synci, but the default can be overridden by configuring GCC with --with-synci. 13214 When compiling code for single processor systems, it is generally safe to use "synci". However, on many 13215 multi-core (SMP) systems, it does not invalidate the instruction caches on all cores and may lead to 13216 undefined behavior. 13217 -mrelax-pic-calls 13218 -mno-relax-pic-calls 13219 Try to turn PIC calls that are normally dispatched via register $25 into direct calls. This is only 13220 possible if the linker can resolve the destination at link time and if the destination is within range for 13221 a direct call. 13222 -mrelax-pic-calls is the default if GCC was configured to use an assembler and a linker that support the 13223 ".reloc" assembly directive and -mexplicit-relocs is in effect. With -mno-explicit-relocs, this 13224 optimization can be performed by the assembler and the linker alone without help from the compiler. 13225 -mmcount-ra-address 13226 -mno-mcount-ra-address 13227 Emit (do not emit) code that allows "_mcount" to modify the calling function's return address. When 13228 enabled, this option extends the usual "_mcount" interface with a new ra-address parameter, which has type,